configure apb saradc controller
SARADC_START_FORCE | enable start saradc by sw |
SARADC_START | start saradc by sw |
SARADC_WORK_MODE | 0: single mode, 1: double mode, 2: alternate mode |
SARADC_SAR_SEL | 0: SAR1, 1: SAR2, only work for single SAR mode |
SARADC_SAR_CLK_GATED | enable SAR CLK gate when saradc idle |
SARADC_SAR_CLK_DIV | SAR clock divider |
SARADC_SAR1_PATT_LEN | 0 ~ 15 means length 1 ~ 16 |
SARADC_SAR2_PATT_LEN | 0 ~ 15 means length 1 ~ 16 |
SARADC_SAR1_PATT_P_CLEAR | clear the pointer of pattern table for DIG ADC1 CTRL |
SARADC_SAR2_PATT_P_CLEAR | clear the pointer of pattern table for DIG ADC2 CTRL |
SARADC_DATA_SAR_SEL | 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. |
SARADC_DATA_TO_I2S | 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix |
SARADC_XPD_SAR_FORCE | force option to xpd sar blocks |
SARADC_WAIT_ARB_CYCLE | wait arbit signal stable after sar_done |