Espressif Systems /ESP32-S3 /APB_SARADC /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SARADC_START_FORCE)SARADC_START_FORCE 0 (SARADC_START)SARADC_START 0SARADC_WORK_MODE 0 (SARADC_SAR_SEL)SARADC_SAR_SEL 0 (SARADC_SAR_CLK_GATED)SARADC_SAR_CLK_GATED 0SARADC_SAR_CLK_DIV 0SARADC_SAR1_PATT_LEN 0SARADC_SAR2_PATT_LEN 0 (SARADC_SAR1_PATT_P_CLEAR)SARADC_SAR1_PATT_P_CLEAR 0 (SARADC_SAR2_PATT_P_CLEAR)SARADC_SAR2_PATT_P_CLEAR 0 (SARADC_DATA_SAR_SEL)SARADC_DATA_SAR_SEL 0 (SARADC_DATA_TO_I2S)SARADC_DATA_TO_I2S 0SARADC_XPD_SAR_FORCE 0SARADC_WAIT_ARB_CYCLE

Description

configure apb saradc controller

Fields

SARADC_START_FORCE

enable start saradc by sw

SARADC_START

start saradc by sw

SARADC_WORK_MODE

0: single mode, 1: double mode, 2: alternate mode

SARADC_SAR_SEL

0: SAR1, 1: SAR2, only work for single SAR mode

SARADC_SAR_CLK_GATED

enable SAR CLK gate when saradc idle

SARADC_SAR_CLK_DIV

SAR clock divider

SARADC_SAR1_PATT_LEN

0 ~ 15 means length 1 ~ 16

SARADC_SAR2_PATT_LEN

0 ~ 15 means length 1 ~ 16

SARADC_SAR1_PATT_P_CLEAR

clear the pointer of pattern table for DIG ADC1 CTRL

SARADC_SAR2_PATT_P_CLEAR

clear the pointer of pattern table for DIG ADC2 CTRL

SARADC_DATA_SAR_SEL

1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.

SARADC_DATA_TO_I2S

1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix

SARADC_XPD_SAR_FORCE

force option to xpd sar blocks

SARADC_WAIT_ARB_CYCLE

wait arbit signal stable after sar_done

Links

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